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Academic Year/course: 2017/18

29819 - Digital Electronics


Syllabus Information

Academic Year:
2017/18
Subject:
29819 - Digital Electronics
Faculty / School:
110 - Escuela de Ingeniería y Arquitectura
326 - Escuela Universitaria Politécnica de Teruel
Degree:
440 - Bachelor's Degree in Electronic and Automatic Engineering
444 - Bachelor's Degree in Electronic and Automatic Engineering
ECTS:
6.0
Year:
2
Semester:
Second semester
Subject Type:
Compulsory
Module:
---

4.1. Assessment tasks (description of tasks, marking system and assessment criteria)

IN ZARAGOZA

 

Course grading

The course is evaluated according to the following items:

-       Mid-term exam (CP)

-       Final exam (CE)

-       Laboratory classes (CL)

The final grade (CG) is obtained using the following equations:

CGaux = 0.8xCT + 0.2xCL, where CT = max{0.2xCP + 0.6xCE, 0.8xCE}, then:

CG = CGaux if CL>4 and CT>4, otherwise CG = min{4, CGaux}

 

IN TERUEL

The course is graded following these rules:

 

COURSE PERIOD:

Laboratory sessions: (grade CL 0 to 10). It accounts for a 25% of the final grade. A minimum of 4 is required to pass the subject.

 

OFFICIAL CALL (EXAM PERIOD):

  • Written exam (theory and problems): grade CT 0 to 10 puntos. It accounts for the 75% of the final grade. A minimum of 4 is required to pass the subject.

  • Laboratory exam: grade CL 0 to 10 puntos. It accounts for the 25% of the final grade. A minimum of 4 is required to pass the subject. This exam is compulsory only for those students who did not obtain a minimum of 4 in CL during the course period.

TOTAL GRADE: If the student has a grade of at least 4 in CL and CT, the final grade will be obtained from CL and CT with the weights indicated above. Otherwise, the student will fail and the grade will be obtained as the minimum of these two values: 4 and 0.75xCT+0.25xCL.

5.1. Methodological overview

The methodology followed in this course is oriented towards achievement of the learning objectives. It is based on participation and the active role of the student favors the development of communication and decision-making skills. A wide range of teaching and learning tasks are implemented, such as lectures, exercises and problems, laboratory sessions, and tutorials.

Students are expected to participate actively in the class throughout the semester.

Classroom materials will be available via Moodle. These include a repository of the lecture notes used in class, the course syllabus, as well as other course-specific learning materials.

Further information regarding the course will be provided on the first day of class.

5.2. Learning tasks

In EINA, Zaragoza:

The course includes 6 ECTS organized according to:

- Lectures (1.8 ECTS): 45 hours.

- Laboratory sessions (0.6 ECTS): 15 hours.

- Guided assignments (0.8 ECTS): 20 hours.

- Autonomous work (2.6 ECTS): 65 hours.

- Assessment (0.2 ECTS): 5 hours.

 

In EUP, Teruel:

Course structure: 2 hours of lectures and 1 hour of problems each week, plus several laboratory sessions (about 15 hours in total), acoording to the schedule of the EUPT. Students will work in groups of two in the laboratory, and the lab reports will be prepared in groups too.

5.3. Syllabus

In EINA, Zaragoza:

 

The course will address the following topics:

 

Theory sessions

Topic 1. Fundamentals of Digital Electronics.

Topic 2. Combinational Logic Circuits.

Topic 3. Sequential Logic Circuits.

Topic 4. Technologies of Digital Circuits.

 

Laboratory sessions

Session 1. Fire-alarm circuit design.

Session 2. BCD to Seven-segment decoder design.

Session 3. Liquid level indicator circuit design.

Session 4. 2-digit BCD counter design using an FPGA.

Session 5. State-machine design using an FPGA.

Session 6. PWM generation to control a servo motor using an FPGA.

 

In EUP Teruel:

 

Syllabus:

  • Fundamentals of logic systems
  • Characteristics of digital circuits
  • Combinational logic
  • Introduction to VHDL
  • Codification and error detection
  • Lacthes and registers
  • Programmable Logic Devices
  • Sequential logic
  • Counters and its applications

Laboratory sessions:

  • Properties of CMOS circuits
  • Combinational circuits in VHDL
  • Monostables and astables with the 555
  • Sequential circuits in VHDL
  • Counters in VHDL (I)
  • Counters in VHDL (II)
  • Design of complex systems

5.4. Course planning and calendar

Lectures run for 3 weekly hours. Laboratory sessions will take place every 2 weeks (6 sessions in total) and last 2.5 hours each.

 

For further details concerning the timetable, classroom and further information regarding this course please refer to the EINA website (eina.unizar.es) in Zaragoza or EUPT in Teruel.

5.5. Bibliography and recommended resources

All course materials are posted on Moodle.

Moodle will be also used to communicate announcements and is where students will submit laboratory reports.

 

Basic references:

  • J.I. Artigas, L.A. Barragán, C. Orrite, I. Urriza, “Electrónica Digital. Aplicaciones y problemas con VHDL”, Prentice-Hall, 2002.
  • J. F. Wakerly, "Digital Design. Principles and Practices", 4ª Edición, Pearson Education Inc., 2006.

Other references:

  • T. L. Floyd "Fundamentos de Sistemas Digitales", 9º Edición, Pearson Educación, 2006.
  • J.I. Artigas, L.A. Barragán, C. Orrite, “Aplicaciones y Problemas de Electrónica Digital”, Prensas Universitarias de Zaragoza. Colección Textos Docentes, 2007.
  • T. Pollán, "Electrónica Digital", Prensas Universitarias de Zaragoza. Colección Textos Docentes, 3ª edición, 2007. Disponible en http://diec.cps.unizar.es/~tpollan/
  • Pollán Santamaría, Tomás. Electrónica digital. I, Sistemas combinacionales / Tomás Pollán Santamaría. 3ª ed. Zaragoza : Prensas Universitarias de Zaragoza, 2007
  • Pollán Santamaría, Tomás. Electrónica digital. II, Sistemas secuenciales / Tomás Pollán Santamaría. 3ª ed. Zaragoza : Prensas Universitarias de Zaragoza, 2007
  • Pollán Santamaría, Tomás. Electrónica digital. III, Microelectrónica / Tomás Pollán Santamaría. 3ª ed. Zaragoza : Prensas Universitarias de Zaragoza, 2007
  • Pollán Santamaría, Tomás. Electrónica digital. IV, Tecnología CMOS / Tomás Pollán Santamaría. 3ª ed. Zaragoza : Prensas Universitarias de Zaragoza, 2007
  • Guía de usuario de la placa de FPGA “Spartan-3 Board” utilizada en el laboratorio.
  • Catálogos de circuitos integrados de los diversos fabricantes (web de los fabricantes).